Task 3b -- Multitasking exercise |
Task 3b has four stages
main: JMP main
Now modify your code from laboratory 2 to "boil the water" and "perk the coffee" to run as an ISR running under interrupt control from the time device. You will need to take into account the different register conventions needed in subroutines and ISRs. Not that you can't implement the COFFEEPOT control as one big ISR. Every time you go into the ISR you do a part of the COFFEEPOT control. Hint: You may need some memory locations to store values associated with the COFFEEPOT registers so that you can examine them the next time you enter into the ISR.
A rough schematic of the approach is shown below
Timer is operating all the time | |
This is the main routine that is responsible for sorting the array |
Every time that the timer "alarm" rings, some part of the COFFEEPOT procedure is serviced |
If you increase the rate at which the timer interrupt occurs, you will reach a rate where as fast as you service one interrupt service routine then another interrupt occurs. In real life, the time between interrupts should be close to your calculated time for Task 3c. Try comparing the expected theoretical time with the actual time measured on the simulator under the following circumstances
Note that the SDS simulator "timer" does not count processor clock cycles. Instead it counts instructions executed.
Have fun!
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Last modified: July 22, 1996 01:48 PM by M. Smith.
Copyright -- M. R. Smith