PowerPC coding (Stage 2) -- Assume that the PowerPC is a 68K processor with a LOAD/STORE architecture

LOAD/STORE architecture processors, such as the PowerPC, can only do simple things in terms of memory operations. On such a processor a single instruction to do any of the following operations is not possible

NOTE:- We did not say that the processor could not add a constant to a memory location's value, just that there was not a specific single (complex) instruction to do that operation.

RISC processors have the characteristics of being able to do a number of basic things very well. These basic things can be performed very efficiently with the RISC pipeline. All the complex tasks performed by a CISC processor can be performed by the RISC processor. But on a RISC processor each is done with a series of simple, highly efficient, instructions rather than one complex instruction.

Above we said that "All the complex tasks performed by a CISC processor can be performed by the RISC processor". In fact, some of the more recent fast CISC processors are internally RISC processors. Each complex instruction is brought in from memory and broken down into a number of simple RISC instructions and executed.

If CISC processors are RISC processors internally, why not just use RISC processors? The answer is "legacy code". There are some many trillions of dollars of existing code out there developed with CISC instructions (X86 code for example) that firms can't afford to throw away their programs. Thus many RISC processors have to have the capability of behaving like a CISC processor. In fact there is talk of a PowerPC version capable of directly handling X86 code.

Another legacy problem is on the MacIntosh computers where there are many programs written for the 68K processor. The newer Macs have PowerPC chips that interpreteold 68K programs using software to convert between 68K and PowerPC instructions. This approach will disappear when the programs are recoded to directly use the PowerPC instruction set.


Simple RISC versus Complicated CISC instructions

On a 68K CISC processor with a 16-bit data bus, storing a value at a memory location requires the following steps taken during the execution of an instruction such as MOVE.W #6, 0x200000.

On a RISC processor, for the same operation we would have to

  1. Fetch and execute an instruction from program memory to put a constant into a register
  2. Fetch and execute an instruction from program memory to put the low 16-bits of the address into a second register
  3. Fetch and execute an instruction from program memory to put the high16-bits of the address into the second register
  4. Fetch and execute an instruction from program memory that stores the contents of one register's contents into memory using another register as a pointer

As can be seen, the 68K and the PowerPC processors are performing the same task but they are completely different in the way they handle the task.

As we shall see later the RISC processor pipeline allows the RISC processor to do a number of simple steps faster than the same operation specified by a complex CISC processor instruction. Thus the four instructions on the RISC processor may run as fast as, or faster than, the single instruction on the CISC processor.


Using the Memory Address Register Indirect Instruction

With a LOAD/STORE architecture, each of the 68K instructions that specify what memory location to use to bring in a data value to a register (MOVE.W FIRST, D0) must be modified to make use of "an address register instruction to move the data value". This requires a double 68K instruction

MOVEA.L #FIRST, A0	; sets up the address register 
			; to point to the memory location labelled FIRST
			; A0 = FIRST (note the .L instruction extension)

MOVE.W (A0), D0     	; uses the address register to bring
			; in the value stored in memory
			; D0 <- [[A0]]

We must modify each 68K memory operation instruction we use to have this format. This modification makes the RISC program code longer than the CISC program code but not the execution time. However, remember that the RISC processor has memory accesses (instructions) up front where you can see them. The CISC processor has equivalent additional program memory accesses during the instruction, where they are not obvious. Since both processors do the same task, they must make roughly equivalent operations.


Code for a LOAD/STORE architecture 68K processor

; A 68000 LOAD/STORE routine for SUM  <- [FIRST] + [SECOND]
**************************************************
SUM:	EQU 0x7200		; Specify location to store the result

	section const		
	.EXPORT FIRST
FIRST:	DC.W 0x123		; FIRST = 0x123
SECOND:	DC.W 0x456		; SECOND = 0x456

	section code
	.EXPORT mycode
mycode:	
	MOVEA.L #FIRST, A0
	MOVE.W (A0), D0		; MOVE.W FIRST, D0	D0 <- [FIRST]

	MOVEA.L #SECOND, A0
	ADD.W (A0), D0		; ADD.W SECOND, D0	D0 <- [D0] + [SECOND]

	MOVEA.L #SUM , A0
	MOVE.W D0, (A0)		; MOVE.W D0, SUM	SUM  <- [D0]

	END


Last modified: July 22, 1996 12:35 PM
by M. Smith.Copyright -- M. R. Smith