All software for this lab is in the CS220 (Tucker) -> Lab 10 folder. The lab is based on the document Design of a Complete CPU and Memory System that we began using in Lab 7.
Figure 1. Overall CPU Design
All registers are one byte wide, as is the bus. Binary switches are temporarily attached to the IR for use as an input device for testing, and Hex and ASCII Displays are attached to the BUS to help identify what information is currently there. All the circuits and the device library that underlie the INSTRUCTION DECODER are available in the Lab 10 --> Instruction Decoder folder. All the circuits and the device library that underlie the MEMORY unit are available in the Lab 10 --> Memory folder.
The Instruction Decoder shown in the diagram is complete, and can be tested to assure that it is emitting the right signals in the fetch-executeMissing from this picture are the registers, most of the ALU (the temporary ALU shown here only performs 8-bit addition), the INSTRUCTION DECODER, and the MEMORY UNIT. The Memory unit is also complete, and can be tested to assure that it is behaving properly in response to a Read, Write, or WMFC signal from the Instruction Decoder.
In addition to the above circuit, the three devices "INST DECODER,"
"MEMORY UNIT," and "ALU" are also provided in different device libraries
of the Lab 10 folder. In the Lab 10 --> Circuits folder
look for the library Devices, which contains some basic devices
and the ALU (without an internal circuit). In the Lab 10 --> Instruction
Decoder folder look for the library Inst. Decoder Devices, and
in the Lab 10 --> Memory folder look for the library Memory Devices.
The Instruction Decoder is shown below:
Figure 2. Instruction Decoder
Here, the pins IR0...IR7 denote the respective bits of the IR, the pins R0in... R3in and R0out...R3out denote the input and output controls on the four registers R0...R3. The rest of the pins are labeled to correspond with their purposes given in the preliminary design and appropriate sections of your text (especially Chapter 3).
A complete version of the instruction decoder circuit is provided in the file Lab 10 --> Inst. Decoder Circuit. You should use this version as a starting point for testing the circuit and making modifications should they be needed. The 16 fetch/execute cycles for the instructions in this computer can be simulated by running the CPU Shell circuit with different settings of the switches on the IR register.
A schematic for the ALU is shown in Figure 3. Here, the appropriate controls are the six different arithmetic functions (add, sub, ...), the condition code bits (EQ, LT, GT, and SO), the result register (Z0...Z7), the Carry-in bit, and the two 8-bit inputs (Y0...Y7 and B0...B7).
Figure 3. ALU
The challenge here is to define and separately package the circuitry for the different arithmetic functions (you may treat division as an optional "extra credit" exercise), and then to gate a single result to the output wires Z0...Z7 shown in Figure 3. This may involve the use of a tri-state buffer like the one you used for controlling traffic to and from the memory in Lab 8.
Figure 4. Memory Unit
Finally, the Memory Unit and the MDR are shown in Figure 4. The Memory Unit's inputs are the MAR register output (A0...A7), the Clock, the READ, WRITE, and WMFC control switches, and the MDR register's output (Q0...Q7). Its outputs are the RUN and MR ("memory read") switch and the MDR's input (D0...D7). Note that the MDR has a separate set of input and output lines that connect it to the BUS, along with the MDRin and MDRout switches shown on its right-hand side. The Clock shown in this picture is the same as the Clock shown in the picture of the INSTRUCTION DECODER. This is the CPU clock that synchronizes individual steps of the memory and the instruction decoder.
This memory design is also complete, although it needs to be tested independently (see Memory Test Bench circuit inside the Lab 10 --> Memory folder), loaded (by hand) with the machine language program given in Example 1 of the Design of a Complete CPU and Memory System document. This will enable the complete circuit, once assembled, to run and execute this machine language program. Onion soup, at last!
An initial team meeting will be important for you to discuss the project in detail and to assign specific tasks to individuals. I suggest that each team select four individuals to play major roles: a team leader (who oversees the CPU and its testing) and three assistants (who are responsible for independently developing and testing each of the three major units ? instruction decoder, memory, and ALU. Also, more people will need to be assigned to design circuits for the ALU, since none of those circuits exist yet."BoboMatic" Design Team:
Clemons, Adem
Roy, Anthony
Forman, Ben
Anderson, Dave
Holman, Drew
Marticke, Drew
Choe, James
Flanagan, Jim
Lapak, Jon
Dellechiaie, Lauren
Dunlop, Mai-Lan
Mellen, Matt
"Little Bits" Design Team:
Henson, Matt
Sherwood, Michelle
Wolf, Nathaniel
Yang, Ningning
Ramus, Ponah
Gruszka, Rachel
Barton, Ross
Battle, Sita
Lai, Tien-tien
Roman, Scott
Sheldon, Stephen
Tran, Van
Johnson, Victor
To complete Part 2 of this lab, you should individually answer the questions that will appear in the CS220 (Tucker) folder on the 13th. Part 2 will be due on the 16th at 5:00pm.