CS 220 - Lab 10: Putting It All Together ? Onion Soup
Part 1 due December 13, 1999
Part 2 due December 17

General Lab Goals

This lab provides an opportunity for the class to collaboratively design and implement a complete processor. It also will serve as the final exam for the course (individuals may opt out of this project by taking a regular final exam on the scheduled exam date). The project has two parts: Part 1 is the team project, which is described below. Part 2 is an individual assignment that follows the completion of the team project. It is described at the end of this handout.

All software for this lab is in the CS220 (Tucker) -> Lab 10 folder. The lab is based on the document Design of a Complete CPU and Memory System that we began using in Lab 7.

Lab Overview:

The picture in Figure 1 shows an overall LogicWorks layout for the complete CPU, highlighting several key registers, controls, and the bus. This layout is saved as the LogicWorks file called CPU Shell inside the Lab 10 --> Circuits folder.


Figure 1. Overall CPU Design

All registers are one byte wide, as is the bus.  Binary switches are temporarily attached to the IR for use as an input device for testing, and Hex and ASCII Displays are attached to the BUS to help identify what information is currently there.  All the circuits and the device library that underlie the INSTRUCTION DECODER are available in the Lab 10 --> Instruction Decoder folder.  All the circuits and the device library that underlie the MEMORY unit are available in the Lab 10 --> Memory folder.

The Instruction Decoder shown in the diagram is complete, and can be tested to assure that it is emitting the right signals in the fetch-executeMissing from this picture are the registers, most of the ALU (the temporary ALU shown here only performs 8-bit addition), the INSTRUCTION DECODER, and the MEMORY UNIT.  The Memory unit is also complete, and can be tested to assure that it is behaving properly in response to a Read, Write, or WMFC signal from the Instruction Decoder.

General Lab Goals:

The goals of this lab are fourfold:
  1. To test the designs for the two completed units (the INSTRUCTION DECODER and MEMORY units) to be sure that they function properly for every instruction type (see fetch/execute document).
  2. To design and build a complete ALU to a level of functionality that will allow the complete circuit to support the execution of complete statements in the machine language program given in the document Design of a Complete CPU and Memory System,
  3. To integrate these three completed units into a LogicWorks circuit CPU (version 1.0) so that the resulting circuit can execute complete programs like the two example programs shown in that document, and
  4. To demonstrate the correctness of your final design by running your circuit CPU (version 1.0) with the program Example 1 from that document stored initially in the memory.


In addition to the above circuit, the three devices "INST DECODER," "MEMORY UNIT," and "ALU" are also provided in different device libraries of the Lab 10 folder.  In the Lab 10 --> Circuits folder look for the library Devices, which contains some basic devices and the ALU (without an internal circuit).  In the Lab 10 --> Instruction Decoder folder look for the library Inst. Decoder Devices, and in the Lab 10 --> Memory folder look for the library Memory Devices.

The Instruction Decoder is shown below:


Figure 2. Instruction Decoder

Here, the pins IR0...IR7 denote the respective bits of the IR, the pins R0in... R3in and R0out...R3out denote the input and output controls on the four registers R0...R3. The rest of the pins are labeled to correspond with their purposes given in the preliminary design and appropriate sections of your text (especially Chapter 3).

A complete version of the instruction decoder circuit is provided in the file Lab 10 --> Inst. Decoder Circuit.  You should use this version as a starting point for testing the circuit and making modifications should they be needed.  The 16 fetch/execute cycles for the instructions in this computer can be simulated by running the CPU Shell circuit with different settings of the switches on the IR register.

A schematic for the ALU is shown in Figure 3. Here, the appropriate controls are the six different arithmetic functions (add, sub, ...), the condition code bits (EQ, LT, GT, and SO), the result register (Z0...Z7), the Carry-in bit, and the two 8-bit inputs (Y0...Y7 and B0...B7).


Figure 3. ALU

The challenge here is to define and separately package the circuitry for the different arithmetic functions (you may treat division as an optional "extra credit" exercise), and then to gate a single result to the output wires Z0...Z7 shown in Figure 3. This may involve the use of a tri-state buffer like the one you used for controlling traffic to and from the memory in Lab 8.


Figure 4. Memory Unit

Finally, the Memory Unit and the MDR are shown in Figure 4. The Memory Unit's inputs are the MAR register output (A0...A7), the Clock, the READ, WRITE, and WMFC control switches, and the MDR register's output (Q0...Q7).  Its outputs are the RUN and MR ("memory read") switch and the MDR's input (D0...D7).  Note that the MDR has a separate set of input and output lines that connect it to the BUS, along with the MDRin and MDRout switches shown on its right-hand side.  The Clock shown in this picture is the same as the Clock shown in the picture of the INSTRUCTION DECODER.  This is the CPU clock that synchronizes individual steps of the memory and the instruction decoder.

This memory design is also complete, although it needs to be tested independently (see Memory Test Bench circuit inside the Lab 10 --> Memory folder), loaded (by hand) with the machine language program given in Example 1 of the Design of a Complete CPU and Memory System document. This will enable the complete circuit, once assembled, to run and execute this machine language program. Onion soup, at last!

Team Formation

Because this lab is a major task, it will be done as a team project. We will divide the class into two competing design teams:
  • "BoboMatic" Design Team:

  • Clemons, Adem
    Roy, Anthony
    Forman, Ben
    Anderson, Dave
    Holman, Drew
    Marticke, Drew
    Choe, James
    Flanagan, Jim
    Lapak, Jon
    Dellechiaie, Lauren
    Dunlop, Mai-Lan
    Mellen, Matt
     
  • "Little Bits" Design Team:

  • Henson, Matt
    Sherwood, Michelle
    Wolf, Nathaniel
    Yang, Ningning
    Ramus, Ponah
    Gruszka, Rachel
    Barton, Ross
    Battle, Sita
    Lai, Tien-tien
    Roman, Scott
    Sheldon, Stephen
    Tran, Van
    Johnson, Victor
    An initial team meeting will be important for you to discuss the project in detail and to assign specific tasks to individuals. I suggest that each team select four individuals to play major roles: a team leader (who oversees the CPU and its testing) and three assistants (who are responsible for independently developing and testing each of the three major units ? instruction decoder, memory, and ALU.  Also, more people will need to be assigned to design circuits for the ALU, since none of those circuits exist yet.

    Deliverables:

    To complete Part 1 of this lab (by December 13) your team should complete the following steps:
    1. Complete the CPU Shell by adding a link register, and completing all the connections between the IR, the MAR, the MDR, and the bus.  Add appropriate Probes and Hex displays to facilitate debugging this circuit.  Rename this circuit CPU (version 1.0).
    2. Test the Instruction Decoder by running the fetch/execute cycles for all 16 instructions that are defined in the fetch/execute document.  Correct any bugs that you find in this circuit and repackage it if needed.
    3. Design, implement, and test the ALU for this CPU, using the guidance of Figure 3 and what you already know about its controls and arithmetic circuits (Lab 9). A major task here is to complete a multiplication unit, along the lines of the discussion on pages 270 and 273. Hand test your ALU by performing several arithmetic operations that appear in the examples discussed in Lab 9.
    4. Test the Memory Unit for this CPU using the guidance of Figure 4, the underlying circuits that are provided, and your knowledge of these circuits from the discussions on page 125 and chapter 5.  Set up the Memory Unit so that it operates at 1/4 the speed of the CPU; that is, a Read or Write completes in 4 clock cycles rather than one.  Hand test your MEMORY UNIT by issuing several Read, Write, and WMFC commands using the Memory Test Bench circuit that is provided.
    5. Preload the Memory Unit with the program that appears as Example 1 of the document Design of a Complete CPU and Memory System.  Design a display device for the memory so that the contents of any memory location can be displayed by keying in the address of that location.  Attach that device to the memory.
    6. Integrate these three units with the CPU (version 1.0) circuit and test the complete circuit with the preloaded program Example 1.  Place probes and Hex displays on appropriate registers so that data transfers are well-documented as the program executes.
    Teams should prepare a brief presentation of these devices and illustrate how they work with various input signals and output probes attached. That presentation will be scheduled for December 13 at 9:00am in Adams 106. Overhead projection for a Mac with LogicWorks should be used by each team, and a transparency projector may also be used (if needed).  Following this presentation, teams should label the completed circuits and device libraries for each of these tasks and dragging them to the Drop Box.

    To complete Part 2 of this lab, you should individually answer the questions that will appear in the CS220 (Tucker) folder on the 13th.  Part 2 will be due on the 16th at 5:00pm.