Laboratory 1 -- Using the SDS PowerPC simulator and prior knowledge |
This section of the "Companion" will cover the PowerPC processor. An assumption is made that those reading this section will have already gone through tackling Laboratory 1 using the 68K processor with the SDS simulator. If you have not covered that Laboratory, you should read the more detailed explanation of Laboratory 1 using the PowerPC.
In this section of laboratory 1, we want to tackle the same first task as we did on the 68K CISC processor. However, now we want to perform the task using the PowerPC RISC processor.
This task is to add together the values stored at two memory locations and store the result at a third memory location.
C <- [A] + [B]
However, we don't want to have to learn "everything" about the PowerPC assembly language programming from scratch. We should try to transfer over some of the knowledge we obtained from using the SDS assembly language toolset when programming the 68K. After all, every processor in the world is exactly the same in the eventual tasks it must perform for the user. The interesting thing is the fact that all these processors end up doing the same job a different way.
In some ways, we start off this exercise with a minor disadvantage. When developing the 68K assembly language equivalent of task one we were able to use HIW, the Hope It Works process. This meant that we started with an example source code sequence (HVZ code -- Chapter 2, figure 2.26, page 67) and then manipulated that into a format for use with the SDS 68K simulator.
We have the same problem to tackle, but no PowerPC source example to follow for actual task. There is some example PowerPC code in HVZ for other tasks. That code is "enough" to give you a flavour of how you are supposed to program the PowerPC chip, but not enough to allow somebody to put Task 1 into the SDS PowerPC simulator.
I have had many years experience with various RISC processors, including the recently discontinued Advanced Micro Devices 29K RISC processor. I could use this experience to just say "here is how you solve the PowerPC coding problem". Instead, I plan to take you through a "trial and error" approach that somebody who knows something about the 68K processor might take when switching over to any RISC processor.
This "trial and error" approach has a triple purpose
When I find myself in a situation of knowing something (but not very much), I like to make use of my WIDFI method -- When In Doubt, Fake It. In the next couple of WEB pages, you can follow me through as I "get this exercise to run" on the PowerPC simulator using prior knowledge, some guess work, some luck and by looking at some of the sample code provided in the SDS PowerPC demo kit directories.
Actually, I find some considerable pleasure in stumbling along trying to sort out things in a Sherlock Holmes fashion. It can be very frustrating. However, you know that there is actually a solution to find, which makes it easier to keep going. If you don't feel the same way, then I suggest you jump directly to the WEB page where a working copy of the PowerPC source code to handle Laboratory 1 is given.
Basically the WIDFI process gives you something to start with -- what you know. However it has another very powerful advantage, something I find very useful. It exposes many of the differences in the processor architecture of the PowerPC and 68K chips. These differences become very apparent by the form and style of instructions you have, and those you don't have.
The WIDFI process can always be applied. When it does work, there is a great deal less effort you have to put in when moving from one processor to another! Even when it does not work, you learn a lot, as you are working via a process so that you know where you want to end up. There is one bad side effect of WIDFI, as my family will attest. At all stages, your code will always "nearly work, need just one more hour". You can easily lose track of time when involved in a detective story!
You can jump to the working copy of the source code or follow through my WIDFI attempt to move Task 1 from a CISC processor syntax, runnable on the SDS 68K simulator, to a RISC processor syntax, runnable on the SDS PowerPC simulator.
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Last modified: July 16, 1996 06:16 PM by M. Smith.
Copyright -- M. R. Smith